Integrated semiconductor memory devices, for example DRAM (Dynamic Random Access Memory) semiconductor memory devices, include a multiplicity of circuit components on a memory chip. FIG. 1 shows an integrated semiconductor memory device 200 comprising a memory cell array 210 comprising memory cells SZ. In the case of DRAM memory cells, a memory cell includes a storage capacitor SC and a selection transistor AT. The memory cells are in each case arranged at a crossover point between a word line WL and a bit line BL.
In order to carry out a read access, a read command LK is applied to a control terminal S220 of a control circuit 220. An address is applied to an address terminal A200, and is buffer-stored in an address register 230. After the control circuit 220 has detected the read command LK at its control terminal S220, a memory cell selected by the address buffer-stored in the address register 230 is activated for the read access. For selection of the memory cell defined by the address, a row decoder 250 selects a row line (word line) within the memory cell array 210. For this purpose, a high level of a word line control voltage VPP is fed in onto the selected word line.
The selection transistor AT, which is embodied as an n-channel field-effect transistor in FIG. 1, is controlled into the on state by the high level of the word line control voltage VPP, with the result that the storage capacitor SC of the memory cell SZ is conductively connected to the connected bit line BL.
A column decoder 240 is provided for selection of the bit line BL connected to the activated memory cell SZ. The bit line selected by the column decoder 240 is subsequently connected to a sense amplifier (not illustrated in FIG. 1). The sense amplifier amplifies the potential on the bit line which has formed on the bit line after the connection of the storage capacitor SC due to the activated selection transistor AT to a low voltage level VBL or a high voltage level VBH. Consequently, a datum DQ having a high potential level or a datum DQ having a low potential level is generated at the data terminal D200.
In order to carry out a write access to the memory cell SZ, the write command SK is applied to the control terminal S220 of the control circuit 220. By virtue of the address applied to the address terminal A200, the row decoder 250 selects the word line connected to the memory cell to be read and the column decoder 240 selects the bit line connected to the memory cell to be read. As a result of the driving of the selected word line with the high potential of the word line control voltage VPP, the selection transistor AT of the selected memory cell is controlled into the on state. As a result of the driving of the bit line BL with a high potential level of the bit line voltage VBH, a one level can be stored in the memory cell. As a result of the driving of the bit line BL with the low potential of the bit line voltage VBL, by contrast, a datum having a zero level can be stored in the memory cell SZ. In this case, the potential states VBH and VBL respectively, are generated by the sense amplifier on the bit line BL in a manner dependent on the data DQ present at the data terminal D200.
The control circuit 220 has a supply voltage terminal V220 for application of a supply voltage VB. Likewise, the column decoder 240 has a supply voltage terminal V240 and the row decoder 250 has a supply voltage terminal V250 for application of the supply voltage VB. The supply voltage VB is provided by a controllable voltage generator 284 at an output terminal A284.
The integrated semiconductor memory device furthermore has controllable voltage generators 281, 282 and 283. The controllable voltage generator 281 generates at an output terminal A281 the high potential of the word line control voltage VPP for controlling the selection transistor AT into the on state. The controllable voltage generator 282 generates at an output terminal A282 the low potential of the bit line voltage VBL, which is fed in for the purpose of storing the zero level into the memory cell SZ onto the bit line BL. The controllable voltage generator 283 generates at an output terminal A283 the high potential of the bit line voltage VBH, which is fed in for the purpose of storing a one level into the memory cell SZ onto the bit line BL.
The voltage generators 281, 282, 283 and 284 generate the voltages VPP, VBL, VBH and VB from an internal supply voltage Vint fed to them by a further controllable voltage generator 270. The controllable voltage generator 270 is connected to a supply voltage terminal V200 for application of an external supply voltage Vext. It generates the stabilized internal supply voltage Vint from the external supply voltage Vext.
In order to be able to compensate for manufacturing tolerances, the controllable voltage generator 270 is embodied in trimmable fashion. Using a control signal AWS fed to it at a control terminal S270, the level of the internal supply voltage can thus be varied. However, the level of the internal supply voltage Vint cannot be increased arbitrarily. An excessively high voltage would lead, for example, in the case of circuit components on the memory chip of the integrated semiconductor memory device, to degradation effects such as hot carrier effects, for example, with the result that the service life of transistors of the integrated semiconductor memory device, for example, would be reduced.
For specific types of integrated semiconductor memories, for example semiconductor memories which are used for graphics applications, a long lifetime of circuit components on the memory chip is dispensed with since developments advance very rapidly in this field, so that the products in this segment are also already obsolete very rapidly and are replaced by newer memories. Thus, at the present time the use of semiconductor memories for graphics applications is in the region of approximately 5years. The speed and performance of integrated semiconductor memories provided for graphics applications are increased in a targeted manner by trimming up the internal supply voltage Vint. The internal supply voltage is trimmed up usually by activation of so-called trimming options within an on-chip voltage generator system of the integrated semiconductor memory device.
In FIG. 1, by way of example, a memory circuit 260 comprising memory elements, for example fuse elements 261, is provided for setting the trimming options. In integrated semiconductor memories provided for graphics applications, for example, specific fuse elements of the memory circuit 260 are activated during the manufacturing process. The state of the fuse elements of the memory circuit 260 is evaluated by an evaluation circuit 290. In a manner dependent on the activated fuse elements, the evaluation circuit 290 generates a control signal AWS, which is fed to the control terminal S270 of the controllable voltage generator 270. Consequently, it is possible to generate an internal supply voltage Vint lying above the internal supply voltage usually used for driving the controllable voltage generators 281, 282, 283 and 284. As a result the voltage generators also generate greater output voltages VPP, VBL, VBH and VB derived from the increased internal supply voltage.
One disadvantage in the case of this method, however, is that, as early as during the manufacturing of the integrated semiconductor memories, it is necessary to define whether the voltage generators 270, 281, 282, 283 and 284 present on the memory chip generate increased voltages. This early dedication is already effected in the context of the wafer test, in which usually by activation of laser fuses, the on-chip voltages are trimmed to the values determined for the respective target application. However, this necessitates high logistical outlay in the area of product planning.
Since the state of the laser fuses is only one-time programmable, such integrated semiconductor memories furthermore have a lack of flexibility. Thus, dynamic voltage regulation of the on-chip voltages cannot be achieved. It is desirable, however, to reduce the level of the internal supply voltage in the case of low capacity utilization of the semiconductor memory, in the case of few memory accesses per unit time. Consequently, in the case of present-day integrated semiconductor memories, a high electrical power loss occurs as a result of a lack of flexibility in the setting of the internal voltages or as a result of the static predefinition of the internal voltages.